Занятость:
Полная

Опыт работы:
от 5 года(лет)

График работы:
Полный день

Требования:
• ph.D. Or m.S. In electronics engineering, computer science, mathematics, physics, or related areas
• experience in industry-leading design tools including hspice, hsim, cadence schematic capture, and other layout tools
• at least 1-year of layout experience is preferred
• io characterization and modeling
• basic knowledge of esd and latch-up
• signal integrity and noise analysis
• programming language experience such as c, perl, etc.

Должностные обязанности:
Job summary • io cell design and/or layout
• chip-level logic design and/or layout
• familiar with drc/lvs verification
• functional and/or timing
verification
responsibility / duty • development of general purpose io library
• customer-specific io circuit design, layout, and verification
• perform logic design, lvs / drc verification, functional and timing verification

• analog circuit design and/or layout
• signal integrity and noise analysis